The present invention relates to a data processor for executing instructions in a pipelined and parallel fashion, and more particularly to a data processor which simultaneously decodes two instructions and executes them in a parallel and pipelined fashion.
In a prior art large scale general purpose computer, instructions are executed in a pipelined fashion to execute different instructions in an overlapped manner so that the execution speed of an instruction sequence is effectively increased. In order to improve speed, various techniques have been proposed. For example, in JP-A-60-17538, in order to execute an instruction which requests operations for two memory operands, two address adders are provided so that addresses of the two memory operands are simultaneously calculated. In JP-A-58-176751, two pipelined instruction execution units simultaneously (or parallelly) decode two instructions in one instruction sequence to parallelly execute them. In JP-A-59-32045 (or corresponding U.S. Pat. No. 4,626,989), in order to improve the above parallel decode technique, if the two instructions cannot be executed in parallel because the result of execution of the first instruction to be executed is used by the second instruction, then the second instruction is executed following the first instruction in the same pipelined instruction execution unit as that for the first instruction.
In the prior art parallel decode technique, each of the two pipelined instruction execution units needs an address generator, an operand read memory and an operation unit. When a data processor is constructed, the operation units and other units are provided in duplicate. Thus, investment in hardware is large, and the control configuration is complex. Since the operation unit comprises a plurality of units which perform various operations, the circuit scale thereof is large.